Sr. Memory Architect

Hod Hasharon, Israel

A senior memory architect, with at least 10 years of volatile or non-volatile semiconductor memory design experience

A senior memory architect to lead the development of Novel NVM modules in advanced nodes using state-of-the-art EDA tools
Proven ability to lead a memory design from the architecture exploration phase, through block level design & layout up to full module assembly, verification & characterization
Interaction with product marketing & customers to analyze & propose memory architectures meeting the needs of the customer

Knowledgeable in all aspects of memory circuit design, analog design, timing & power optimization, and Design for Test
Experience in memory timing & power characterization
Proficiency in Low-Power, Low-Voltage & Low-Leakage design practices
Experience in advanced geometries and understanding of different technologies (FDSOI, FinFet)
Experience with memory compilers is an advantage
Proficient in Cadence virtuoso schematic design, Spice simulators, Fast-Spice & mixed-signal simulators, High-Sigma analysis tools, Parasitic extraction & modeling, Memory characterization

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